Pages of Understanding the Apple II - Ch. 4 -The 6502 Microprocessor

[ all issues ] [ all topics ]

• page 4-1
  • the 6502 microprocessor
• page 4-2
  • 6502 signals
  • address and r/w
  • clockpulses - phase 0, phase 1, phase 2
  • data bus
• page 4-3
  • schematic: 6502 connections in the apple ii
• page 4-4
  • interrupts - IRQ and NMI
  • READY
  • reset
  • SET OVERFLOW
  • SYNC
• page 4-5
  • 6502 connections in the apple
  • 6502 memory usage
• page 4-6
  • 6502 clockpulse relationships
  • 6502 timing in the apple ii
• page 4-7
• page 4-8
  • some worst case 6502 specifications
• page 4-9
  • experimental 6502 timing relationships
• page 4-10
  • apple programming
  • reading the disk input port using device select
• page 4-11
• page 4-12
• page 4-13
  • cycle stealing DMA
  • DMA in the apple
• page 4-14
• page 4-15
  • 6502 interrupts in the apple
  • RESET
• page 4-16
  • NMI and IRQ
• page 4-17
  • the BREAK instruction
• page 4-18
• page 4-19
  • priority among interrupts
• page 4-20
  • 6502 instruction details
• page 4-21
• page 4-22
  • 6502 instructions
• page 4-23
  • 6502 instruction cross reference
• page 4-24
  • D MAnual controller
• page 4-25
  • schematic: D MAnual controller
• page 4-26
  • operation of soft switchs from D MAnual controller
• page 4-27
  • a screen mode controller
  • selection of 16K RAM card or IIe bank switched RAM from D MAnual controller
• page 4-28
  • an NMI based single stepper
  • schematic: an NMI based single stepper
• page 4-29
• page 4-30
  • assembler listing: NMI stepper routines
• page 4-31
• page 4-32
  • design concept for a hardware breakpoint generator